Método de fabricación de estructuras de puerta de transistores MOSFET sobre semiconductores III-V - Information about the patent

Método de fabricación de estructuras de puerta de transistores MOSFET sobre semiconductores III-V
  • Country: Spain
  • Filing date: 22/06/2012
  • Request number:

    P201200664

  • Publication number:

    ES2435866

  • Grant date: 13/05/2014
  • Status: Concesión
  • Inventors:
    María Ángela PAMPILLÓN ARCE
    Carmina CAÑADILLA SOTO
    Pedro FEIJOO GUERRO
    Enrique SAN ANDRÉS
    Álvaro DEL PRADO MILLÁN
    María Luisa LUCÍA MULAS
  • Information of the applicant:
    UNIVERSIDAD COMPLUTENSE DE MADRID
  • Information of the representative:
    Joaquín PLUMET ORTEGA
  • Publication's International Patent Classification:
    H01L 21/8232,H01L 21/335,C23C 14/35,
  • Publication's International Patent Classification:
    H01L 21/8232,H01L 21/335,C23C 14/35
  • Expiration date:

National patent for "Método de fabricación de estructuras de puerta de transistores MOSFET sobre semiconductores III-V"

This application has been made by

UNIVERSIDAD COMPLUTENSE DE MADRID

through the representative

JOAQUÍN PLUMET ORTEGA

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This information is public since it was obtained from the BOPI (Official Bulletin of Industrial Property). According to article 13 of the intellectual property law, the acts and resolutions of public bodies are not subject to intellectual property rights. In addition, according to article 2.b of the data protection law, the consent of the owner of the data is not required to communicate said data to a third party in the case of data collected from sources accessible to the public (the BOPI is a public document).
The products and services protected by this patent are:
H01L 21/8232 - H01L 21/335 - C23C 14/35

Publications:
ES2435866 (23/12/2013) - A1 Solicitud de patente con informe sobre el estado de la técnica
ES2435866 (21/05/2014) - B2 Patente de invención con examen previo

Events:
On the date 22/06/2012 Registro Instancia de Solicitud took place
On the date 26/06/2012 Admisión a Trámite took place
On the date 26/06/2012 1001P_Comunicación Admisión a Trámite took place
On the date 02/07/2012 IET1_Petición Realización IET took place
On the date 06/11/2012 Suspenso en Examen Formal y Técnico took place
On the date 19/11/2012 Publicación Suspenso Examen Formal took place
On the date 14/12/2012 3007 registro contestación al suspenso Examen Formal took place
On the date 01/02/2013 Continuación del Procedimiento took place
On the date 13/02/2013 Publicación Continuación del Procedimiento e Inicio IET took place
On the date 01/08/2013 Realizado IET took place
On the date 12/08/2013 Informe Estado de la Tecnica took place
On the date 14/08/2013 1109P_Comunicación Traslado del IET took place
On the date 23/12/2013 Publicación Solicitud con IET took place
On the date 23/12/2013 Publicación Folleto Solicitud con IET (A1) took place
On the date 20/02/2014 Reanudación Procedimiento con Examen Previo took place
On the date 26/02/2014 Publicación Reanudación Procedimiento con Examen Previo took place
On the date 13/05/2014 Concesión took place
On the date 13/05/2014 1253P_Notificación Concesión por Examen Previo took place
On the date 21/05/2014 Publicación concesión Patente EP took place
On the date 21/05/2014 Publicación Folleto Concesión took place
On the date 09/10/2014 Entrega título took place


Information on the registration of national patent by Método de fabricación de estructuras de puerta de transistores MOSFET sobre semiconductores III-V with the number P201200664

The registration of national patent by Método de fabricación de estructuras de puerta de transistores MOSFET sobre semiconductores III-V with the number P201200664 was requested on the 22/06/2012. It is a record in Spain so this record does not offer protection in the rest of the countries. The registration Método de fabricación de estructuras de puerta de transistores MOSFET sobre semiconductores III-V with the number P201200664 was requested by UNIVERSIDAD COMPLUTENSE DE MADRID through the services of the Joaquín PLUMET ORTEGA. The registration of [modality] by Método de fabricación de estructuras de puerta de transistores MOSFET sobre semiconductores III-V with the number P201200664 is classified as H01L 21/8232,H01L 21/335,C23C 14/35 according to the international patent classification.

Other inventions requested by UNIVERSIDAD COMPLUTENSE DE MADRID

It is possible to know all the inventions requested by UNIVERSIDAD COMPLUTENSE DE MADRID, among which is the record of national patent by Método de fabricación de estructuras de puerta de transistores MOSFET sobre semiconductores III-V with the number P201200664. If you want to know more inventions requested by UNIVERSIDAD COMPLUTENSE DE MADRID click here.

Other inventions requested in the international patent classification H01L 21/8232,H01L 21/335,C23C 14/35.

It is possible to know inventions similar to the field of the technique concerned. The registration of national patent by Método de fabricación de estructuras de puerta de transistores MOSFET sobre semiconductores III-V with the number P201200664 is classified with the classification H01L 21/8232,H01L 21/335,C23C 14/35 so if you want to know more records with the classification H01L 21/8232,H01L 21/335,C23C 14/35 click here.

Other inventions requested through the representative JOAQUÍN PLUMET ORTEGA

It is possible to know all the inventions requested through the JOAQUÍN PLUMET ORTEGA among which is the record national patent by Método de fabricación de estructuras de puerta de transistores MOSFET sobre semiconductores III-V with the number P201200664. If you want to know more inventions requested through the JOAQUÍN PLUMET ORTEGA click here.

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